DRAM memory cells are conventionally comprised of a MOS transistor and a capacitor. Despite this simple structure, DRAM memory cells are difficult to miniaturise, the difficulty mainly residing in the reduction of the size of the capacitors. To overcome this difficulty, memory cells comprised of a single transistor, without capacitor, have been elaborated, the MOS transistor having a junction-insulated body or a insulator-insulated body in semiconductor on insulator (SOI) or semiconductor on nothing (SON) technologies. In these so-called “1T-DRAM” memory cells, the memory function corresponds to a storage of charges in the body of the transistor.
1T-DRAM memory cells suffer for the most part from considerable drawbacks, among which may be cited a limited retention duration, a high consumption, a low differentiation between the two memory states, a low operating speed, the impossibility of reducing the thickness of the transistor body which has to ensure the simultaneous presence of two types of charge carriers (electrons and holes), and/or manufacturing difficulties.
The “A2RAM” memory cell architecture, described in the patent FR2958779 and the article [“Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates”, N. Rodriguez et al., IEEE Transactions on Electron Devices, Volume 58, Issue 8, 2011], is on the contrary distinguished by a controlled consumption, a wide programming window, a simple control and the absence of super-coupling, that is to say the impossibility of having the two types of charge carriers in a thin silicon layer (typically of thickness less than 20 nm).
FIG. 1 is a sectional view schematically representing an A2RAM type memory cell.
The A2RAM memory cell is comprised of a MOS transistor resting on an insulator layer 1, typically the buried oxide layer of a SOI type substrate 2. In a conventional manner, the MOS transistor comprises a source region 3 and a drain region 4 strongly doped of a first conductivity type, for example of N type, and separated by a body region 5. The source 3 and drain 4 regions are respectively in contact with source 6 and drain 7 metallisations, connected respectively to source S and drain D terminals. The body region 5 is surmounted by a gate 8 connected to a gate terminal G through a gate metallisation 9. The gate 8 is electrically insulated from the body region 5 by a dielectric layer 10, typically a gate oxide.
The particularity of this MOS transistor is that the body region 5 is divided in its thickness into an upper body region 5a on the side of the gate 8 and a lower body region 5b in the vicinity of the insulator layer 1. The upper body region 5a, also called “channel region” or “storage node”, is weakly doped of a second conductivity type opposite to the first type, i.e. of P type in this example. The lower body region 5b is doped of the same conductivity type as the source and drain 3-4 regions, i.e. of N type. It is commonly called “conductive bridge” since it electrically connects, in the absence of bias on the gate, the source 3 and the drain 4.
The operating principle of this memory cell is as follows. An information bit is memorised by controlling the quantity of majority charge carriers stored in the upper body region 5a. Thus, two memory states may be distinguished: the logic state ‘1’ when the upper body region 5a contains majority charge carriers (holes in the case of a P type doped upper body region 5a) and the logic state ‘0’ when the upper body region 5a is empty of majority charge carriers.
The information stored in the memory cell is read by measuring the current that circulates in the resistance formed by the source 3, the lower body region 5b and the drain 4 (all three N type doped). To do so, a negative potential is applied to the gate 8 and a slightly positive potential is applied to the drain 4. In the case where a ‘0’ state has been programmed, that is to say that no charge is stored in the upper body region 5a, no current circulates in the upper body region 5a because the transistor is off (there is thus no formation of the conductive channel). Furthermore, the negative potential of the gate 8 depletes the lower body region 5b which thus does not allow current to pass. On the contrary, when the ‘1’ state has been programmed, the positive charges stored in the upper body region 5a form a screen to the negative potential of the gate 8 and a current of electrons circulates in the (not depleted) region of the lower body 5b. 
Two ways of programming the A2RAM memory cell in the ‘1’ state exist. These are based on distinct physical phenomena for generating the majority charge carriers: impact ionisation (II) in the upper body region 5a and band to band tunnelling effect between the drain 4 and the upper body region 5a. 
FIG. 2A schematically represents the writing of a ‘1’ in the memory cell of FIG. 1 (NMOS transistor) by impact ionisation in the upper body region 5a. A relatively high positive potential VD, for example 1 V to 3 V, is applied to the drain 4 of the transistor, whereas the gate 8 is brought to a positive potential VG (typically 1 V). The source 3 of the transistor is permanently connected to a reference potential, in general zero for the sake of simplicity. These potentials have the effect of biasing the transistor in the on state, and more particularly in saturation regime. Thus, a conductive channel 11 forms in the upper body region 5a and a current of electrons circulates from the source 3 to the drain 4. Given that the difference in potentials between the source 3 and the drain 4 is relatively high, a strong electric field reigns in the pinch zone of the conductive channel 11. Under the effect of this electric field, electrons in circulation create electron-hole pairs by impact in the upper body region 5a. The electrons created are collected by the drain 4 and contribute to the drain current I, whereas the holes remain in the upper body region 5a, trapped by the potential barriers due to the PN junctions between the source 3 and the upper body region 5a, between the drain 4 and the upper body region 5a, and between the upper body region 5a and the lower body region 5b. 
This first programming mode has the advantage of being rapid (programming time of the order of one ten of nanoseconds), to the detriment of a high electrical consumption. Furthermore, the strong electric field that reigns in the pinch zone of the channel 11 is responsible for problems of information retention and of reliability of the transistor. Electrons subjected to the electric field are indeed trapped in the gate oxide 10, which can lead to a failure of the memory cell.
FIG. 2B schematically illustrates the writing of a ‘1’ in the same memory cell by band to band tunnelling effect. In this second programming mode, the transistor is biased in the off state. A highly negative potential VG, comprised between −2.5 V and −3 V, is applied to the gate 8 while the drain 4 is taken to a positive potential VD, for example 1.2 V. The potential applied to the source 3 is still zero. This bias of the transistor modifies the energy band diagram between the drain 4 and the upper body region 5a, thereby allowing the passage, by tunnel effect, of holes from the conduction band of the drain 4 to the valence band of the upper body region 5a (and the passage of electrons from the valence band of the region 5a to the conduction band of the drain 4).
Unlike the first programming mode (impact ionisation), programming by band to band tunnelling effect does not consume much energy, because the transistor is in the “off” state during writing. The band to band tunnelling effect programming time is in contrast much longer, of the order of 1 μs for the aforementioned potential values. The generation of holes by band to band tunnelling effect is all the greater when the electric field in the upper body region 5a is high. Thus, to reach a programming time comparable to that of impact ionisation, it would be necessary to greatly increase the drain-gate voltage in order to maximise the electric field.
Thus, with conventional programming modes, it is observed that it is impossible to reconcile high programming speed and low electrical consumption.